General purpose on-chip processors have become ubiquitous today. These processors range from extremely small and low power micro-controllers (used in motor controls, robotic platforms, home-appliances, etc.) to hefty and high-performance multi-core processors (used in servers and supercomputers). However, the growth of modern domain-specific languages (like Caffe, Tensorflow, etc.) and the need for more specialized features like machine-learning, enhanced security, etc. has forced the industry to look beyond general purpose solutions and towards mass-customization. While a large number of companies today can develop custom ASICs (Application Specific Integrated Chips) and license specific silicon blocks from chip-vendors to develop a customized SoCs (System on Chips), at the heart of every design is the processor and the associated hardware. To serve modern workloads better, these processors also need to be customized, upgraded, re-designed and augmented suitably. This requires that vendors/consumers have access to relevant processor variants and the flexibility to make modifications and ship them at an endurable cost.
Today, a fair share of the processor market is dominated by just a few giants like Intel, ARM, AMD, etc. Each of these companies have an impressive IP portfolio of processors catering to various market trends. Almost all of the IP offerings of these companies fall under a licensing model which varies significantly. For example, Intel licenses its ISA only to limited users like AMD. ARM on the other hand offers a broad of range of licenses from ISA to architectural licenses. Apart from just license fees, these companies also charge royalties on devices using their IPs. Having sustained a successful IP model, today some of these licenses can go up to 1-10\$ Million in addition to strict NDAs which may restrict the user from making any proprietary changes or even publishing relevant numbers. All these aspects of the licensing model, while benefiting the respective companies, has made is difficult for consumers to develop truly customized solutions for modern day workloads. Some of these customizations cater to too low a market sector for the giants themselves to invest in, thereby prohibiting growth and novelty.
In essence, the closed-source IP model in the processor community is proving to be a hindrance to build scalable solutions. A similar struggle in the software industry against closed-source IP led to the rise of the open-source Linux kernel in the 1990s. Since then the software community has seen a plethora of open-source software and tool-chains which have been adopted by industry and academia both. The hardware community however, hasn't seen such a revolution yet and is probably in dire need of the same. An open-source processor ecosystem will not only boost customization but also allow bright minds of the industry and academia to collaborate and provide a stable and viable framework competent enough with modern-day products. SHAKTI, an open-source initiative by IIT-Madras (Indian Institute of Technology Madras) is primarily aimed at building such open-source processor development ecosystems which can equip the community with enough ammunition to build custom and industrial grade processors without the hassle of licensing, NDAs, royalties or any other sort of restrictions.
The SHAKTI Program
The SHAKTI Processor Program, was started as an academic initiative back in 2014 by the RISE group at IIT-Madras. Realizing the limitations of the processor industry mentioned above, the initiative aimed at not only creating open-source industrial grade processors but also building associated components of a bigger ecosystem - like interconnect fabrics, scalable verification platforms, peripheral IPs, etc. - which enables rapid adoption of the processors. Some of the major highlights of the program which make it a viable option for adoption are:
Source code of all the components of the SHAKTI ecosystem are open under the 3 part BSD license. This means a user could freely use, modify and circulate the source code without having to sign any NDAs, licenses or even notify the authors as long as the license header file remains. The SHAKTI program itself will not assert any patents and thereby removes the burden of paying royalties as well.
The processors of the SHAKTI ecosystem are build using the open-source RISC-V ISA. RISC-V has been designed for modularity and extensions, thereby perfectly fitting the prologue of "customization". The ISA also comes with a complete software stack, including compilers, operating systems, and debuggers, which are open source and thus also modifiable. Since the ISA does not dictate micro-architectural features, the software and hardware can be maintained by two complete different entities and yet be compatible. This allows for great re-usability and sharing of code-base across the community.
The SHAKTI processors and the front-end (RTL) designs are developed using the open-source High Level Synthesis (HLS) language:Bluespec System Verilog (BSV). BSV equips the user to develop extremely modular and parameterized modules with defined interfaces. This feature facilitates the user to focus and modify only the designs of interest without having to break the rest of the flow. Today there exists a free bsv-parser which the community can use to develop open/proprietary compilers for BSV.
Academia now has access to a real world working prototypes of processors which they can play with for free. This enables them to depart from the world of "simulators" and "emulation models" and try out their research and ideas in practice. They are no longer tied down by strict NDAs on publishing and can thereby participate more actively in shaping the future of the processor industry.
A typical process of acquiring ISA or architectural licenses from companies like ARM can vary anywhere between 6-12 months. This increases the time-to market for the consumers. SHAKTI, can immensely reduce this time by avoiding such formalities and providing a powerful modular framework allowing small tech start-ups to only modify components of interest rather than building a solution from scratch.
With minds from all over the community pouring in ideas and solutions, SHAKTI has the potential to become a state-of-the-art offering quickly
An open-source ecosystem such as SHAKTI promotes a mix-and-match environment where users can plug-in different open-source or proprietary IPs and innovate on new ideas and projects.
Being completely open-source, it is close-to-impossible for external entities to add back-doors and black-boxes. This is of particular interest to strategic sectors of a countries like India, which today depend on black-box solutions provided by industries which are headquartered in foreign countries.
SHAKTI can also enable the software community drastically. Fearing strong patent lawsuits, software developers who own licensed HW IPs for development are forced to release only binaries rather source code and also provide minimal documentation. This leaves the software Libre community in dangling state, spending months and even years \emph{"picking up pieces"}.
In addition to the above arguments, a combination of the open-source processor ecosystems such as SHAKTI and a fabrication entity like TSMC, which is offering upto 100 small tests chips on its latest technology node for only 30,000\$, can virtually enable any project with real-chips for their final validation at drastically low costs and time.
Architectural Features
Overview
- In-order 3 stage 32/64 bit microcontroller supporting a subset of RISC-V ISA.
- Low area and power consumption - operational frequency of < 200MHz on silicon.
- Optimized variants for FPGA based soft-cores.
- AXI4/AXI4-Lite/TileLink peripherals supported
- Positioned against ARM’s M class cores
Basic Specifications
- Open source IP supporting RV32/64 - IMAC.
- Optional Direct-mapped caches for instruction and data.
- Supports Machine and User-modes only.
- User-mode trap handling is optional.
- Push button flow to generate variants and subsets of ISA.
- Optimized sequential Multiplier and Divider for ASICs and FPGAs
- OpenOCD based SoC debug support through JTAG.
- OS Ports: FreeRTOS, Zephyr
Source code
https://gitlab.com/shaktiproject/cores/e-class
